Issue faced trying to sample MISO data to master SPI through 2ff synchronizer.... When SCLK(spi generated clock) frequency is half of PCLK(system clock) , realise that there are 2 transfers before the
Issue faced trying to sample MISO data to master SPI through 2ff synchronizer.... When SCLK(spi generated clock) frequency is half of PCLK(system clock) , realise that there are 2 transfers before the